Analysis of Clock Jitter in Continuous-Time Sigma-Delta Modulators

One of the factors limiting the performance of continuous-time sigma-delta modulators (CTSDM) is clock jitter. This jitter can be classified as synchronous and accumulated/longterm jitter. A clock that is derived from a phase-lock loop (PLL) contains both types of jitter. In this paper, we present a framework that can be used to obtain the output spectrum in the presence of jitter, either synchronous or accumulated, or a combination of both. First, a general expression for the output power spectral density of the CTSDM in the presence of clock jitter is derived. Based on this, analytical expressions for the output power spectral density are obtained for particular cases of synchronous and long-term jitter. These are validated against behavioural simulations.